2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
V TT + 2 x Y mV
V TT + Y mV
tLZ(DQS), tLZ(DQ)
V OH
2x X
X
V OH - X mV
V OH - 2x X mV
V TT
actual wave
tHZ(DQS), tHZ(DQ)
V TT
Y
V TT - Y mV
V TT - 2 x Y mV
T1 T2
2x Y
V OL
T1 T2
V OL + 2x X mV
V OL + X mV
Start driving point = 2 × T1 - T2
End driving point = 2 × T1 - T2
7. Measured from the point when DQS/DQS# begins driving the signal, to the point when
DQS/DQS# begins driving the first rising strobe edge.
8. Measured from the last falling strobe edge of DQS/DQS# to the point when DQS/DQS#
finishes driving the signal.
9. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK/CK# crossing.
10. CKE input hold time is measured from CK/CK# crossing to CKE reaching a HIGH/LOW
voltage level.
11. Input setup/hold time for signal (CA[9:0], CS#).
12. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. The letter b is appended to the boot parameter
symbols (for example, t CK during boot is t CKb).
13. Mobile LPDDR2 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
14. The output skew parameters are measured with default output impedance settings
using the reference load.
15. The minimum t CK column applies only when t CK is greater than 6ns.
16. Timing derating applies for operation at 85?C to 105?C when the requirement to derate
is indicated by mode register 4 op-code (see the MR4 Device Temperature (MA[7:0] =
04h) table).
17. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
148
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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